EProClock Programmable Technology
參數(shù)資料
型號: SL28EB740AZIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 15/21頁
文件大?。?/td> 0K
描述: IC CLK CK505 TNLCK/TPCLF 56TSSOP
標準包裝: 2,000
系列: EProClock®
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: Intel CPU 服務器
輸入: 時鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:16
差分 - 輸入:輸出: 無/是
頻率 - 最大: 166.67MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
SL28EB740
DOC#: SP-AP-0006 (Rev. AC)
Page 3 of 21
EProClock Programmable Technology
EProClock is the world’s first non-volatile programmable
clock. The EProClock technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
36
SRC6 / CPU2_ITP
O, DIF
Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CKPWRGD assertion = SRC6
ITP_EN = 1 @ CKPWRGD assertion = CPU2
37
CPU1#
O, DIF
Complement differential CPU clock output
38
CPU1
O, DIF
True differential CPU clock output
39
VDD_CPU
PWR
3.3V Power supply
40
CPU0#
O, DIF
Complement differential CPU clock output
41
CPU0
O, DIF
True differential CPU clock output
42
GND_CPU
GND
Ground
43
SCLK
I
SMBus compatible SCLOCK
44
SDATA
I/O
SMBus compatible SDATA
45
CPU_STP#*
I, PU
3.3V-tolerant input for stopping CPU outputs (internal 100K-ohm pull-up)
46
PCI/SRC_STP#*
I, PU
3.3V-tolerant input for stopping PCI and SRC outputs (internal 100K-ohm
pull-up)
47
XOUT
O
25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
48
XIN / CLKIN
I
25.00MHz Crystal input or 3.3V, 25MHzClock Input
49
GND_SUSPEND
GND
Ground for REF clock and WOL support
50
25MHz
O
25MHz reference output clock
51
VDD_SUSPEND
PWR
3.3V Power Supply for REF clock and power to support WOL
52
CKPWRGD/WOL_STP#/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled /
Asynchronous active low input pin that stops all outputs except free running
25MHz when WOL_EN = “1” (Byte 1 bit 1)
This pin becomes a real-time active low input for asserting power down (PD#)
when WOL_EN = “0” (Byte 1 bit 1).
53
VDD_14
PWR
3.3V Power supply
54
14.318M / FSC**
I/O, PD Fixed 14.318MHz clock output/3.3V-tolerant input for CPU frequency selection
(internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
55
GND_14
GND
Ground
56
NC
No Connect.
56-TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
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