參數(shù)資料
型號(hào): SL28EB740AZIT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 5/21頁(yè)
文件大?。?/td> 0K
描述: IC CLK CK505 TNLCK/TPCLF 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: EProClock®
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時(shí)鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:16
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 166.67MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28EB740
DOC#: SP-AP-0006 (Rev. AC)
Page 13 of 21
PCI/SRC_STP# Assertion
The PCI/SRC_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI/SRC_STP# going LOW is 10 ns (tSU).
(See Figure 6.) The PCIF and SRC clocks are affected by this
pin if their corresponding control bit in the SMBus register is
set to allow them to be free running. For SRC clocks assertion
description, please refer to CPU_STP# description.
.
PCI/SRC_STP# Deassertion
The deassertion of the PCI/SRC_STP# signal causes all PCI
and stoppable PCIF to resume running in a synchronous
manner within two PCI clock periods, after PCI/SRC_STP#
transitions to a HIGH level. Simlarly, PCI/SRC_STP#
deassertion will cause stoppable SRC clocks to resume
running. For SRC clocks deassertion description, please refer
to CPU_STP# description.
.
Figure 6. PCI/SRC_STP# Assertion Waveform
Figure 7. PCI/SRC_STP# Deassertion Waveform
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