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參數(shù)資料
| 型號： | SLX24C64 |
| 廠商： | SIEMENS AG |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 64千位8192 × 8位串行CMOS EEPROM的，I2C同步2線總線 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大小： | 361K |
| 代理商： | SLX24C64 |
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SLx 24C01/02/P
Semiconductor Group
15
1998-07-27
6
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
Read Operations
6.1
Random read operations allow the master to access any memory location.
Random Read
Figure 11
Random Read
Address Setting
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low on the SDA line.
Now the master transmits the EEPROM address (EEA) to the
EEPROM and the internal address counter is loaded with the
desired address.
After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Transmission of CSR
Transmission of
EEPROM Data
STOP Condition from
Master
Command Byte
CSW
S
P
A
C
K
C
K
A
S
T
A
R
T
T
O
P
S
EEPROM Address
EEA n
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02133
C
K
A
Data Byte
1
0
S
T
R
A
T
S
CSR
Command Byte
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