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| 型號(hào)： | SLX24C64 |
| 廠商： | SIEMENS AG |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 64千位8192 × 8位串行CMOS EEPROM的，I2C同步2線總線 |
| 文件頁(yè)數(shù)： | 20/27頁(yè) |
| 文件大?。?/td> | 361K |
| 代理商： | SLX24C64 |
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SLx 24C01/02/P
Semiconductor Group
20
1998-07-27
7.2
For writing or erasing a protection bit, the data of the respective page have to be known
by the master. The data of the page are not affected by the write or erase procedure of
the protection bit. The
I
2
C-Bus protocol is shown in
figure 15
for protection bit write and
figure 16
for protection bit erase.
Protection Bit Write and Erase
Figure 15
Sequence for Protection Bit Write
Figure 16
Sequence for Protection Bit Erase
The first command byte CSW followed by the control byte EEA addresses the page to
be protected. The second command byte CSW (identical content of first CSW) is
followed by the control byte CTW = 01
H
for protection bit write or CTE = 03
H
for protection
bit erase. Depending on CTx, the addressed protection bit will be either written or
erased.
T
O
P
S
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02142
S
R
T
A
T
S
Command
Byte
CSW
EEPROM
Address
EEA n
Byte n
Data
Byte n+1
Data
Byte n+7
Data
C
K
A
1
0
0
0
0
0
0
0
...
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
R
T
A
T
S
S
Command
Byte
CSW
Control
Byte
CTW
P
T
O
P
S
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02143
S
R
T
A
T
S
Command
Byte
CSW
EEPROM
Address
EEA n
Byte n
Data
Byte n+1
Data
Byte n+7
Data
C
K
A
1
1
0
0
0
0
0
0
...
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
R
T
A
T
S
S
Command
Byte
CSW
Control
Byte
CTE
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