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參數(shù)資料
| 型號： | SLX24C64 |
| 廠商： | SIEMENS AG |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 64千位8192 × 8位串行CMOS EEPROM的，I2C同步2線總線 |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 361K |
| 代理商： | SLX24C64 |
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SLx 24C01/02/P
Semiconductor Group
18
1998-07-27
7
Each page (8 bytes) in the Data Memory can be protected against unintended data
changes by an associated protection bit. The protection bit memory consists of an
additional EEPROM of 16/32 bits (
figure 14
).
Data in the Data Memory can be modified only if the assigned protection bit is erased
(logical state “1”). After writing the data bytes to a page, the protection is achieved by
writing the associated protection bit (logical state “0”). Further changes in the data in a
protected page is possible only after erasing the protection bit.
Page Protection Mode
TM
Figure 14
Data Page and Assigned Protection Memory
A special procedure to write or erase a protection bit guarantees proper activation or
deactivation respectively of page protection. For protection bit write or erase, all 8 data
bytes of the respective page have to be entered for a second time. The data then are
compared internally with the data to be protected, and in case of identity the protection
bit is written or erased respectively.
1
0
2
3
Byte
.
.
.
0
1
2
3
n
Page 0
Page 1
Page 2
Page 3
Page n
Bit
IED02141
Data Memory Area
P
5
6
7
4
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