參數(shù)資料
型號(hào)： SMARTPSE24-KIT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 13/36頁(yè)
文件大小： 0K
描述： KIT EVAL REF 24PORT SPI/UART
標(biāo)準(zhǔn)包裝： 1
主要目的： 電源管理，以太網(wǎng)供電（POE），PSE
已用 IC / 零件： Si3452，Si3482，Si3500
已供物品： 板，線纜，CD
相關(guān)產(chǎn)品： SI3482-A01-GM-ND - IC CTLR POE 24-48PORT PSE 24-QFN
336-1830-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1835-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1829-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1831-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1834-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1844-5-ND - IC POE SWITCH PWR OVER LAN 20QFN
336-1833-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1832-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
Si3452
20
Rev. 1.3
T
a
ble
19.
Si3452
Reg
ister
Ma
p
Ad
dress
Reg
ister
Na
me
T
y
pe
B7
B6
B5
B4
B3
B2
B1
B0
Regist
er
Con
ten
tat
Power
Up
Interrupt
s
0x00
Inter
rupt
R
eg
1
R
O
Ov
er
temp
cha
nge
V
EE
UVLO
change
Port
4
event
P
or
t3
event
P
o
rt
2
event
Port
1
eve
nt
0x0
0
0x01
Inter
rupt
M
ask
1
R
W
D
evi
ce
sta-
tus
mask
t ST
AR
T
mask
tI
CUT
mask
Rgood
C
LS
mask
DET
compl
mask
Disconn
ect
mas
k
Pwr
G
oo
dmask
Pw
rEn
mask
0x8
5
Por
tEvent
s
0x02
P
o
rt
1
Event
s
C
OR
t ST
AR
T
Event
tI
CU
T
Event
R
good
CLS
D
ET
compl
D
isconnect
Ev
Pwr
G
oo
d
Change
PwrEn
Chan
ge
0x0
0
0x03
P
o
rt
2
Event
s
C
OR
t ST
AR
T
Event
tI
CU
T
Event
R
good
CLS
D
ET
compl
D
isconnect
Ev
Pwr
G
oo
d
Change
PwrEn
Chan
ge
0x0
0
0x04
P
o
rt
3
Event
s
C
OR
t ST
AR
T
Event
tI
CU
T
Event
R
good
CLS
D
ET
compl
D
isconnect
Ev
Pwr
G
oo
d
Change
PwrEn
Chan
ge
0x0
0
0x05
P
o
rt
4
Event
s
C
OR
t ST
AR
T
Event
tI
CU
T
Event
R
good
CLS
D
ET
compl
D
isconnect
Ev
Pwr
G
oo
d
Change
PwrEn
Chan
ge
0x0
0
St
a
tu
s
0x06
P
or
t1
S
tatus
RO
PwrGood
S
tatus
Pwr
E
n
able
S
tatus
CLS
S
tat
B2
CL
S
tat
B1
CLS
S
ta
tB
0
DET
S
tat
B2
DET
S
tat
B1
DET
S
ta
tB0
0x
0
0x07
P
or
t2
S
tatus
RO
PwrGood
S
tatus
Pwr
E
n
able
S
tatus
CLS
S
tat
B2
CL
S
tat
B1
CLS
S
ta
tB
0
DET
S
tat
B2
DET
S
tat
B1
DET
S
ta
tB0
0x
0
0x08
P
or
t3
S
tatus
RO
PwrGood
S
tatus
Pwr
E
n
able
S
tatus
CLS
S
tat
B2
CL
S
tat
B1
CLS
S
ta
tB
0
DET
S
tat
B2
DET
S
tat
B1
DET
S
ta
tB0
0x
0
0x09
P
or
t4
S
tatus
RO
PwrGood
S
tatus
Pwr
E
n
able
S
tatus
CLS
S
tat
B2
CL
S
tat
B1
CLS
S
ta
tB
0
DET
S
tat
B2
DET
S
tat
B1
DET
S
ta
tB0
0x
0
Co
nfigu
ra
tion
0x0A
Port
1
C
onfig
R
W
Por
tpriority
PoE+
Discon
En
Por
tMode
B1
Port
Mo
de
B0
00000100
b
0x0B
Port
2
C
onfig
R
W
Por
tpriority
PoE+
Discon
En
Por
tMode
B1
Port
Mo
de
B0
00000100
b
0x0C
Port
3
C
onfig
R
W
Por
tpriority
PoE+
Discon
En
Por
tMode
B1
Port
Mo
de
B0
00000100
b
0x0D
Port
4
C
onfig
R
W
Por
tpriority
PoE+
Discon
En
Por
tMode
B1
Port
Mo
de
B0
00000100
b
0x0E
Por
t1
I
CUT
R
W
B7
B6
B5
B4
B
3
B2
B1
B0
0x
7
5
No
tes:
1.
R
egister
conten
tat
Power
Up
is
shown
fo
rthe
Si3452
Shut
do
wn
Mode
p
art.
Refe
rto
to
or
der
Aut
o
Mode
p
ar
ts
with
dif
fere
nt
default
se
ttings.
T
his
register
can
be
cha
nged
via
th
ehost
.Refer
to
for
re
gister
var
iations.
2.
B0
Alterna
tive
B
tim
ing
is
set
to
0x01
if
using
Alter
native
B
de
tect
timing.
Refer
to
and
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