參數資料
型號: SMARTPSE24-KIT
廠商: Silicon Laboratories Inc
文件頁數: 35/36頁
文件大?。?/td> 0K
描述: KIT EVAL REF 24PORT SPI/UART
標準包裝: 1
主要目的: 電源管理,以太網供電(POE),PSE
已用 IC / 零件: Si3452,Si3482,Si3500
已供物品: 板,線纜,CD
相關產品: SI3482-A01-GM-ND - IC CTLR POE 24-48PORT PSE 24-QFN
336-1830-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1835-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1829-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1831-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1834-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1844-5-ND - IC POE SWITCH PWR OVER LAN 20QFN
336-1833-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1832-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
Si3452
8
Rev. 1.3
Table 8. Port Measurement and Monitoring Specifications
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Port Current Measurement
Offset
IOFFSET
20 mA ≤ IPORT ≤ ICUT. For final
IPORT reading, add offset to% of
reading tolerance.
–5
5
mA
Port Current Measurement
Tolerance
%TOL
–4
4
%
Table 9. SMBus (I2C) Electrical Specifications
VDD = 3.0 to 3.6 V
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Low Voltage
VIL
SCL, SDA pins
0.8*
V
Input High Voltage
VIH
SCL, SDA pins
2.2
V
Output Low Voltage
VOL
SCL, SDA pins,
driving ≤ 8.5 mA
——
0.6
V
Input Leakage Current
IL
SCL, SDA pins
40
A
*Note:
0.85 V for Tj >–10 °C. This ensures compatibility with Si840x isolators with 3 k pull up. For isolator compatibility over
the full temperature range, use Si860x isolators.
Table 10. Address Pin Electrical Specifications*
VDD = 3.0 to 3.6 V
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Low Voltage
VIL
AD0, AD1, AD2, AD3 pins
0.8
V
Input High Voltage
VIH
AD0, AD1, AD2, AD3 pins
0.7 x VDD
——
V
Input Leakage Current
IH, IL
AD0, AD1, AD2, AD3 pins
–10
10
A
*Note:
At power-up, these pins are logic inputs. A 10 k
pull up or pull down resistor is used for address selection. After
address recognition, the pins are used for internal communications.
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