Figure 1. I2C Timing Diagram Table 11. SMBus " />
參數(shù)資料
型號(hào)： SMARTPSE24-KIT
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 36/36頁(yè)
文件大?。?/td> 0K
描述： KIT EVAL REF 24PORT SPI/UART
標(biāo)準(zhǔn)包裝： 1
主要目的： 電源管理，以太網(wǎng)供電（POE），PSE
已用 IC / 零件： Si3452，Si3482，Si3500
已供物品： 板，線(xiàn)纜，CD
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Si3452
Rev. 1.3
9
Figure 1. I2C Timing Diagram
Table 11. SMBus (I2C) Timing Specifications (see Figure 1)
VDD = 3.0 to 3.6 V
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Serial Bus Clock
Frequency
fSCL
0—
400
kHz
SCL High Time
tSKH
600
—
ns
SCL Low Time
tSKL
1.3
—
μs
SCL, SDA Rise Time
tR_SCL
20
—
300
ns
SCL, SDA Fall Time
tF_SCL
20
—
150
ns
Bus Free Time
tBUF
Between START and STOP
conditions.
1.3
—
μs
Start Hold Time
tSTH
Between START and first low SCL.
600
—
ns
Start Setup Time
tSTS
Between SCL high and START
condition.
600
—
ns
Stop Setup Time
tSPS
Between SCL high and STOP
condition.
600
—
ns
Data Hold Time
tDH
200
—
ns
Data Setup Time
tDS
200
—
ns
Time from Hardware or
Software Reset until Start
of I2C Traffic
tRESET
Reset to start condition
—
100
ms
Delay from Event to INT
Pin Low or from Clear-On-
Read to INT Pin High
tINT
——
5
ms
Notes:
1.
Not production tested (guaranteed by design).
2.
All timing references measured at VIL and VIH.
3.
The Si3452 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is
10 sec; so, SCL only needs to be bidirectional for I2C bus speeds over 50 kHz.
SCL
D7
fSCL
tR_SCL
tF_SCL
tSKH
SDA
tSKL
tSTH
tSPS
D6
D5
D4
D3
D0
tDS
tDH
Start Bit
Stop Bit
tBUF
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