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| 型號： | SMJ34020AHT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁數(shù)： | 25/92頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AHT |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
cycle timing examples (continued)
LRDY low at the start of the first Q2 after RAS low (Figure 3) indicates that the memory requires the addition
of wait states. LRDY high at the next Q2 indicates the cycle can continue without inserting more wait states.
PGMD high at the start of Q2 where LRDY is sampled high indicates that this memory does not support
page-mode operation.
LCLCK1
LCLCK2
GI
LAD (SMJ34020A)
(see Note A)
LAD (Memory)
(see Note A)
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Address
Column
Address Subcycle
Wait State
Read Transfer
Data
Row
Q4
(see Note B)
(see Note B)
See clock stretch, page 20.
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD (memory): Output to LAD by the memory.
B. Although they are not internally sampled, PGMD and SIZE16 must be held at a valid level at the
start of each Q2 until LRDY is sampled high.
Figure 3. Local-Memory Read-Cycle Timing (without page mode, with one wait state)
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