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參數(shù)資料
| 型號(hào)： | SMJ34020AHT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS SYSTEM PROCESSOR |
| 中文描述： | 圖形系統(tǒng)處理器 |
| 文件頁(yè)數(shù)： | 8/92頁(yè) |
| 文件大?。?/td> | 1458K |
| 代理商： | SMJ34020AHT |
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SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Pin Functions (Continued)
PIN
DESCRIPTION
NAME
I/O
VIDEO INTERFACE (CONTINUED)
SCLK
I
Serial data clock. SCLK is the same as the signal that drives VRAM serial data registers. SCLK allows the SMJ34020A
to track the VRAM serial-data-register count, providing serial-register transfer and midline-reload cycles. (SCLK can
be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK frequency).
VCLK
I
Video clock. VCLK is derived from a multiple of the video system’s dot clock and is used internally to drive the video
timing logic.
VSYNC
I/O
Vertical sync. VSYNC
is the vertical sync signal that controls external video circuitry. VSYNC can be programmed to
be either an input or an output by modifying a control bit in the DPYCTL register.
As an output, VSYNC is the active-low vertical-sync signal generated by the SMJ34020A’s on-chip video timers.
As an input, VSYNC synchronizes the SMJ34020A video-control registers to externally generated vertical-sync
pulses. The actual synchronization can be programmed to begin at any horizontal line; this allows for any
external pipelining of signals.
Immediately following reset, VSYNC is configured as an input.
I = input, O = output
functional block diagram
Register
File A
HA5–HA31
HBS0–HBS3
HCS
HREAD
HWRITE
HINT
HRDY
HDST
HOE
GI
R0
R1
EMU0
EMU1
EMU2
EMU3
CLKIN
LCLK1
LCLK2
RESET, LINT1,
LINT2
LAD0–LAD31
RCA0–RCA12
DDIN
DDOUT
RAS
CAS0–CAS3
WE
TR/QE
ALTCH
SF
PGMD
SIZE16
LRDY
BUSFLT
CAMD
VSYNC
HSYNC
CSYNC/HBLNK
CBLNK/VBLNK
VCLK
SCLK
27
4
32
13
Host
Address
Latch
Host
Interface
Multi-
Processor
Interface
Emulation
Interface
System
Clocks
Buffer/
Page-mode
Register
MUX
Bus
Control
DRAM/
VRAM
Interface
Bus
Interface
Video
Timing
and
Control
Local
Memory
and
Bus
Timing
I/O
Regs
LRU
ALU
Barrel
Shifter
Microcontrol ROM
Reset and Interrupts
Cache
PC
ST
SP
Decode
4
Register
File B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SMJ34020AHTM32 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SMJ34020AHTM40 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SMJ34020HTM28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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