參數(shù)資料
型號: SMJ34020AHT
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS SYSTEM PROCESSOR
中文描述: 圖形系統(tǒng)處理器
文件頁數(shù): 84/92頁
文件大小: 1458K
代理商: SMJ34020AHT
SMJ34020A
GRAPHICS SYSTEMPROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
84
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multiprocessor-interface timing: GI, ALTCH, RAS, R0 and R1 (see Figure 44)
NO.
’34020A-32
MIN
’34020A-40
MIN
UNIT
MAX
MAX
105
ta(GIV-RQV)
Access time, GI valid after R0 and R1 valid
(see Note 9)
2tQ–40
2tQ–30
ns
105.1
tsu(GIV-CK1H)
Setup time, GI valid before LCLK1 no longer low
(see Note 9)
40
35
ns
106
th(CK1H-GIV)
td(CK2H-RQV)
td(CK2H-RQNV)
Hold time, GI valid after LCLK1 no longer low
0
0
ns
107
Delay time, LCLK2 no longer low to R0 or R1 valid
tQ+15
tQ+13.5
ns
108
Delay time, LCLK2 high to R0 or R1 no longer valid
tQ–15
tQ–13.5
ns
NOTE 9: These timings must be met to ensure that GI is recognized on this clock cycle.
For a SMJ34020A to gain control of the local bus during a given cycle, GI must be low at the start of Q1 (indicating
that the bus arbitration logic is granting the bus to this processor).
GI
R0–R1
LCLK2
LCLK1
106
105
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Valid
Valid
108
107
105.1
See clock stretch, page 20.
Figure 44. Multiprocessor-Interface Timing: GI, ALTCH, RAS, R0 and R1
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