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參數(shù)資料
| 型號： | SN54ABT657A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Transceivers With Parity-Generators/Checkers and 3-State Outputs(八收發(fā)器(帶奇偶發(fā)生器/校驗器)) |
| 中文描述： | 八路收發(fā)器與Parity-Generators/Checkers和三態(tài)輸出（八收發(fā)器（帶奇偶發(fā)生器/校驗器）） |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 219K |
| 代理商： | SN54ABT657A |
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25
°
C
High-Impedance State During Power Up
and Power Down
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
Th
noninverting
checker circuits and control signals. The
transmit/receive (T/R) input determines the
direction of data flow. When T/R is high, data flows
from the A port to the B port (transmit mode); when
T/R is low, data flows from the B port to the A port
(receive mode). When the output-enable (OE)
input is high, both the A and B ports are in the
high-impedance state.
ABT657A
transceivers
buffers
have
eight
with
parity-generator/
Odd or even parity is selected by a logic high or
low level on the ODD/EVEN input. PARITY carries
the parity-bit value; it is an output from the parity
generator/checker in the transmit mode and an
input to the parity generator/checker in the receive
mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low
(even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an
even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is
low, indicating a parity error.
Copyright
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-
ΙΙ
B is a trademark of Texas Instruments Incorporated.
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24
23
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18
17
16
15
14
13
T/R
A1
A2
A3
A4
A5
V
CC
A6
A7
A8
ODD/EVEN
ERR
OE
B1
B2
B3
B4
GND
GND
B5
B6
B7
B8
PARITY
SN54ABT657A . . . JT PACKAGE
SN74ABT657A . . . DW OR NT PACKAGE
(TOP VIEW)
3 2
1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A3
A2
A1
NC
T/R
OE
B1
ODD/EVEN
ERR
PARITY
NC
B8
B7
B6
4
26
14 15 16 17 18
B
G
G
N
B
B
B
A
A
A
N
A
A
SN54ABT657A . . . FK PACKAGE
(TOP VIEW)
V
C
NC – No internal connection
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| SN54ABT8240 | Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器)) |
| SN74ABT8240 | Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器)) |
| SN54ABT8244 | Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器)) |
| SN74ABT8244 | Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器)) |
| SN54ABT828 | 10-Bit Buffers/Drivers With 3-State Outputs(10位緩沖器/驅(qū)動器(三態(tài)輸出)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABT657AFK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
| SN54ABT657AJT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
| SN54ABT7819 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| SN54ABT7819GB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| SN54ABT7819HT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
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