
SN54ABT8240, SN74ABT8240
SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS484 – JULY 1994
Copyright
1994, Texas Instruments Incorporated
3–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
SCOPE
Family of Testability Products
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port
and Boundary-Scan Architecture
Functionally Equivalent to SN54/74F240
and SN54/74ABT240 in the Normal-
Function Mode
SCOPE
Instruction Set:
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP
and HIGHZ
– Parallel-Signature Analysis at Inputs
With Masking Option
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Even-Parity Opcodes
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline Packages (DW), Ceramic
Chip Carriers (FK), and Standard Ceramic
DIPs (JT)
description
The SN54ABT8240 and SN74ABT8240 scan test
devices with octal buffers are members of the
Texas Instruments SCOPE
testability integrated
circuit family. This family of devices supports IEEE
Standard
1149.1-1990
facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.
boundary
scan
to
In the normal mode, these devices are functionally equivalent to the SN54/74F240 and SN54/74ABT240 octal
buffers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the
device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect
the functional operation of the SCOPE
octal buffers.
In the test mode, the normal operation of the SCOPE
octal buffers is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan
test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other
testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8240 is characterized for operation over the full military temperature range of – 55
°
C to 125
°
C.
The SN74ABT8240 is characterized for operation from –40
°
C to 85
°
C.
3 2 1
13 14
5
6
7
8
9
10
11
2A4
TDI
TCK
NC
TMS
TDO
2Y4
1A2
1A1
2OE
NC
1OE
1Y1
1Y2
4
15 16 17 18
1
G
N
2
2
2
1
1
2
N
28 27 2625
24
23
22
21
20
19
12
1
V
2
2
C
SN54ABT8240 . . . JT PACKAGE
SN74ABT8240 . . . DW PACKAGE
(TOP VIEW)
SN54ABT8240 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1OE
1Y1
1Y2
1Y3
1Y4
GND
2Y1
2Y2
2Y3
2Y4
TDO
TMS
2OE
1A1
1A2
1A3
1A4
2A1
V
CC
2A2
2A3
2A4
TDI
TCK
NC – No internal connection
SCOPE and EPIC-
ΙΙ
B are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P