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參數(shù)資料
| 型號： | SN54ABT657A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Transceivers With Parity-Generators/Checkers and 3-State Outputs(八收發(fā)器(帶奇偶發(fā)生器/校驗器)) |
| 中文描述： | 八路收發(fā)器與Parity-Generators/Checkers和三態(tài)輸出（八收發(fā)器（帶奇偶發(fā)生器/校驗器）） |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 219K |
| 代理商： | SN54ABT657A |
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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| SN54ABT657AFK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
| SN54ABT657AJT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
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