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參數(shù)資料
| 型號： | SN54ABTH182646A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With 18 Bit Universal Bus Transceivers( 掃描檢測裝置，帶18位收發(fā)器和寄存器) |
| 中文描述： | 掃描測試設(shè)備與18位通用總線收發(fā)器（掃描檢測裝置，帶18位收發(fā)器和寄存器） |
| 文件頁數(shù)： | 16/37頁 |
| 文件大?。?/td> | 842K |
| 代理商： | SN54ABTH182646A |
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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A
SCAN TEST DEVICES WITH
18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D – AUGUST 1993 – REVISED JULY 1996
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→
BIT 0
MSB
→
LSB
X00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/36-bit mode (PRPG)
X10
Parallel-signature analysis/36-bit mode (PSA)
011
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 51–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 51–48 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are valid only when both bytes of the device are operating in one
direction of data flow (that is, 1OEA
≠
1OEB and 2OEA
≠
2OEB) and in the same direction of data flow (that is,
1OEA
=
2OEA and 1OEB
=
2OEB). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
相關(guān)PDF資料 |
PDF描述 |
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| SN54ABTH1826520A | Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測裝置，帶18位總線收發(fā)器和寄存器) |
| SN74ABTH1826520A | Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測裝置帶18位總線收發(fā)器和寄存器) |
| SN54ABTH18652A | Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測裝置，帶18位總線收發(fā)器和寄存器) |
| SN54ABTH245FK | OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABTH182646AHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS |
| SN54ABTH182652A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS |
| SN54ABTH182652AHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS |
| SN54ABTH18502A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS |
| SN54ABTH18502A_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS |
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