參數(shù)資料
型號(hào)： SN54ABTH182646A
廠商： Texas Instruments, Inc.
英文描述： Scan Test Devices With 18 Bit Universal Bus Transceivers( 掃描檢測(cè)裝置，帶18位收發(fā)器和寄存器)
中文描述： 掃描測(cè)試設(shè)備與18位通用總線收發(fā)器（掃描檢測(cè)裝置，帶18位收發(fā)器和寄存器）
文件頁(yè)數(shù)： 7/37頁(yè)
文件大?。?/td> 842K
代理商： SN54ABTH182646A
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A
SCAN TEST DEVICES WITH
18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D – AUGUST 1993 – REVISED JULY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1149.1-1990. All test instructions, test data, and test control signals are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The function of the TAP controller is to
extract the synchronization (TCK) and state control (TMS) signals from the test bus and generate the
appropriate on-chip control signals for the test structures in the device. Figure 2 shows the TAP-controller state
diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and four test-data registers: a 52-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
Figure 2. TAP-Controller State Diagram
相關(guān)PDF資料
PDF描述
SN54ABTH1826520A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測(cè)裝置，帶18位總線收發(fā)器和寄存器)
SN74ABTH1826520A Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測(cè)裝置帶18位總線收發(fā)器和寄存器)
SN54ABTH18652A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測(cè)裝置，帶18位總線收發(fā)器和寄存器)
SN54ABTH245FK OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABTH245DB OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN54ABTH182646AHV 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SN54ABTH182652A 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
SN54ABTH182652AHV 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
SN54ABTH18502A 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABTH18502A_07 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*