參數(shù)資料
型號(hào)： SN54ABTH182646A
廠商： Texas Instruments, Inc.
英文描述： Scan Test Devices With 18 Bit Universal Bus Transceivers( 掃描檢測(cè)裝置，帶18位收發(fā)器和寄存器)
中文描述： 掃描測(cè)試設(shè)備與18位通用總線收發(fā)器（掃描檢測(cè)裝置，帶18位收發(fā)器和寄存器）
文件頁(yè)數(shù)： 3/37頁(yè)
文件大?。?/td> 842K
代理商： SN54ABTH182646A
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A
SCAN TEST DEVICES WITH
18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D – AUGUST 1993 – REVISED JULY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
In the test mode, the normal operation of the SCOPE
bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin
architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A
PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count
addressing scheme is useful.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The B-port outputs of ’ABTH182646A, which are designed to source or sink up to 12 mA, include 25-
series
resistors to reduce overshoot and undershoot.
The SN54ABTH18646A and SN54ABTH182646A are characterized for operation over the full military
temperature range of –55
°
C to 125
°
C. The SN74ABTH18646A and SN74ABTH182646A are characterized for
operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(normal mode, each 9-bit section)
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
X
DIR
X
CLKAB
↑
X
↑
L
CLKBA
X
↑
↑
L
SAB
X
SBA
X
A1 – A9
Input
Unspecified
B1 – B9
Unspecified
Store A, B unspecified
Store B, A unspecified
X
X
X
X
Input
H
X
X
X
Input
Input
Store A and B data
H
X
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
X
X
H
Output
Input disabled
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
X
X
H
X
Input disabled
Output
Stored A data to B bus
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus pins is stored on every low-to-high transition of the clock inputs.
相關(guān)PDF資料
PDF描述
SN54ABTH1826520A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測(cè)裝置，帶18位總線收發(fā)器和寄存器)
SN74ABTH1826520A Scan Test Devices With 18 Bit Universal Bus Transceivers And Registers( 掃描檢測(cè)裝置帶18位總線收發(fā)器和寄存器)
SN54ABTH18652A Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測(cè)裝置，帶18位總線收發(fā)器和寄存器)
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