參數(shù)資料
型號(hào): SN74ABT8240
廠商: Texas Instruments, Inc.
英文描述: Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器))
中文描述: 掃描測試設(shè)備與八路緩沖器(掃描測試裝置(帶八緩沖器))
文件頁數(shù): 13/19頁
文件大?。?/td> 391K
代理商: SN74ABT8240
SN54ABT8240, SN74ABT8240
SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS484 – JULY 1994
3–13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the device input pins is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output pins on each falling edge of TCK. Figure 6 illustrates the
8-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial
seed value should be scanned into the BSR before performing this operation. Note that a seed value of all zeroes
does not produce additional patterns.
=
=
M
2A4
2Y4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
Figure 6. 8-Bit PSA/PRPG Configuration
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the device input pins is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit binary count-up
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output pins on each falling edge of TCK. Figure 7 illustrates the
8-bit linear-feedback shift-register algorithm through which the signature is generated. An initial seed value
should be scanned into the BSR before performing this operation.
=
=
M
2A4
2Y4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
MSB
LSB
Figure 7. 8-Bit PSA/COUNT Configuration
P
相關(guān)PDF資料
PDF描述
SN54ABT8244 Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器))
SN74ABT8244 Scan Test Devices With Octal Buffers(掃描測試裝置(帶八緩沖器))
SN54ABT828 10-Bit Buffers/Drivers With 3-State Outputs(10位緩沖器/驅(qū)動(dòng)器(三態(tài)輸出))
SN74ABT828 10-Bit Buffers/Drivers With 3-State Outputs(10位緩沖器/驅(qū)動(dòng)器(三態(tài)輸出))
SN54ABT834 8-Bit To 9-Bit Parity Bus Transceivers(8-9奇偶總線收發(fā)器)
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