參數(shù)資料
型號(hào): SN74ABT8240
廠商: Texas Instruments, Inc.
英文描述: Scan Test Devices With Octal Buffers(掃描測(cè)試裝置(帶八緩沖器))
中文描述: 掃描測(cè)試設(shè)備與八路緩沖器(掃描測(cè)試裝置(帶八緩沖器))
文件頁(yè)數(shù): 8/19頁(yè)
文件大小: 391K
代理商: SN74ABT8240
SN54ABT8240, SN74ABT8240
SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS484 – JULY 1994
3–8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 1. Boundary-Scan-Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
17
2OE
15
2A4
7
2Y4
16
1OE
14
2A3
6
2Y3
––
––
13
2A2
5
2Y2
––
––
12
2A1
4
2Y1
––
––
11
1A4
3
1A4
––
––
10
1A3
2
1A3
––
––
9
1A2
1
1A2
––
––
8
1A1
0
1A1
boundary-control register
The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in the basic SCOPE
instruction set. Such operations include
PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations decoded by
the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 00000000010, which selects the PSA test operation with no input masking.
The BCR order of scan is from TDI through bits 10–0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.
Table 2. Boundary-Control-Register Configuration
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
10
MASK2.4
6
MASK1.4
2
OPCODE2
9
MASK2.3
5
MASK1.3
1
OPCODE1
8
MASK2.2
4
MASK1.2
0
OPCODE0
7
MASK2.1
3
MASK1.1
––
––
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation.
During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is illustrated in
Figure 3.
Bit 0
TDO
TDI
Figure 3. Bypass Register Order of Scan
P
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