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參數(shù)資料
| 型號： | SN74ABT8374 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測試裝置(帶八D邊沿觸發(fā)器)) |
| 中文描述： | 掃描測試設(shè)備與八路D型邊沿觸發(fā)正反器（掃描測試裝置（帶八?邊沿觸發(fā)器）） |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 391K |
| 代理商： | SN74ABT8374 |
SN54ABT8374, SN74ABT8374
SCAN TEST DEVICES WITH
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS486 – JULY 1994
3–11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control-Register Opcodes
BINARY CODE
BIT 2
→
BIT 0
MSB
→
LSB
X00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/16-bit mode (PRPG)
X10
Parallel-signature analysis/16-bit mode (PSA)
011
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)
It should be noted, in general, that while the control input BSCs (bits 17–16) are not included in the sample,
toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSC (bit 16 of the BSR) does control the drive
state (active or high impedance) of the selected device output pins.
PSA input masking
Bits 10–3 of the BCR to specify device input pins to be masked from PSA operations. Bit 10 selects masking
for device input pin 8D. Bit 3 selects masking for device input pin 1D. Bits intermediate to 10 and 3 mask
corresponding device input pins in order from most significant to least significant, as indicated in Table 3. When
the mask bit that corresponds to a particular device input has a logic 1 value, the device input pin is masked
from any PSA operation, meaning that the state of the device input pin is ignored and has no effect on the
generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not
masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the device input pins is captured in the shift-register elements of the input BSCs on each rising
edge of TCK. This data is updated in the shadow latches of the input BSCs and applied to the inputs of the normal
on-chip logic. Data in the shift-register elements of the output BSCs is toggled on each rising edge of TCK,
updated in the shadow latches, and applied to the device output pins on each falling edge of TCK.
P
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| SN74ABT841ADBR | 功能描述:閉鎖 10bit Bus D RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74ABT841ADBRE4 | 功能描述:閉鎖 10bit Bus D RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74ABT841ADBRG4 | 功能描述:閉鎖 10B Bus-Interface D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74ABT841ADW | 功能描述:閉鎖 10bit Bus D RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74ABT841ADWG4 | 功能描述:閉鎖 10B Bus-Interface D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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