參數(shù)資料
型號: SN74ABT8374
廠商: Texas Instruments, Inc.
英文描述: Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測試裝置(帶八D邊沿觸發(fā)器))
中文描述: 掃描測試設(shè)備與八路D型邊沿觸發(fā)正反器(掃描測試裝置(帶八?邊沿觸發(fā)器))
文件頁數(shù): 12/19頁
文件大?。?/td> 391K
代理商: SN74ABT8374
SN54ABT8374, SN74ABT8374
SCAN TEST DEVICES WITH
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS486 – JULY 1994
3–12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the output BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the device output pins on each falling edge of TCK. This
data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip
logic. Figure 4 illustrates the 16-bit linear-feedback shift-register algorithm through which the patterns are
generated. An initial seed value should be scanned into the BSR before performing this operation. Note that
a seed value of all zeroes does not produce additional patterns.
=
8D
8Q
7D
6D
5D
4D
3D
2D
1D
7Q
6Q
5Q
4Q
3Q
2Q
1Q
Figure 4. 16-Bit PRPG Configuration
parallel signature analysis (PSA)
Data appearing at the device input pins is compressed into a 16-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs
remains constant and is applied to the device outputs. Figure 5 illustrates the 16-bit linear-feedback
shift-register algorithm through which the signature is generated. An initial seed value should be scanned into
the BSR before performing this operation.
=
=
M
8D
8Q
7D
6D
5D
4D
3D
2D
1D
7Q
6Q
5Q
4Q
3Q
2Q
1Q
Figure 5. 16-Bit PSA Configuration
P
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