參數(shù)資料
型號: SPAKD56366PV120
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 24-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: TQFP-144
文件頁數(shù): 14/147頁
文件大小: 2156K
代理商: SPAKD56366PV120
4-4
DSP56366 Advance Information
MOTOROLA
Design Considerations
PLL Performance Issues
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses
on best-case operation conditions, which is not necessarily a real application case. The typical internal
current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions.
For applications that require very low current consumption, do the following:
Set the EBD bit when not accessing external memory.
Minimize external memory accesses and use internal memory accesses.
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
Connect the unused inputs to pull-up or pull-down resistors.
Disable unused peripherals.
One way to evaluate power consumption is to use a current per MIPS measurement methodology to
minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A
benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test
current measurements, and the following equation to derive the current per MIPS value.
where :
ItypF2 = current at F2
ItypF1 = current at F1
F2 = high frequency (any specified operating frequency)
F1 = low frequency (any specified operating frequency lower than F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1
could be 33 MHz. The degree of difference between F1 and F2 determines the amount
of precision with which the current rating can be determined for an application.
PLL PERFORMANCE ISSUES
The following explanations should be considered as general observations on expected PLL behavior.
There is no testing that verifies these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL
and the internal DSP clock for a given device in specific temperature, voltage, input frequency and MF.
These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz
IMIPS
IMHz
ItypF2 ItypF1
() F2 F1
()
==
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