參數(shù)資料
型號： SPAKD56366PV120
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 24-BIT, 120 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁數(shù)： 2/147頁
文件大?。?/td> 2156K
代理商： SPAKD56366PV120
1-6
DSP56366 Advance Information
MOTOROLA
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.
External Address Bus
External Data Bus
External Bus Control
Table 1-5 External Address Bus Signals
Signal Name
Type
State
during
Reset
Signal Description
A0–A17
Outpu
t
Tri-stated
Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs
that specify the address for external program and data memory accesses.
Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do
not change state when external memory spaces are not being accessed.
Table 1-6 External Data Bus Signals
Signal Name
Type
State during
Reset
Signal Description
D0–D23
Input/Output
Tri-stated
Data Bus—When the DSP is the bus master, D0–D23 are active-
high, bidirectional input/outputs that provide the bidirectional data
bus for external program and data memory accesses. Otherwise,
D0–D23 are tri-stated.
Table 1-7 External Bus Control Signals
Signal
Name
Type
State
during
Reset
Signal Description
AA0–AA2/
RAS0–
RAS2
Outpu
t
Tri-stated
Address Attribute or Row Address Strobe—When defined as AA, these signals can
be used as chip selects or additional address lines. When defined as RAS, these signals
can be used as RAS for DRAM interface. These signals are tri-statable outputs with
programmable polarity.
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