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參數(shù)資料
| 型號： | SPAKD56366PV120 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-BIT, 120 MHz, OTHER DSP, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 16/147頁 |
| 文件大?。?/td> | 2156K |
| 代理商： | SPAKD56366PV120 |
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4-6
DSP56366 Advance Information
MOTOROLA
Design Considerations
Host Port Considerations
very quickly without regard to the clock rate used by the DSP, but the state of the bit could be
changing during the read operation. This is not generally a system problem, because the bit will be
read correctly in the next pass of any host polling routine.
However, if the host asserts HEN for more than timing number 31, with
a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be
stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP
changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits
during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has
significance, the host could read the wrong combination. Therefore, read the bits twice and
check for consensus.
Overwriting the Host Vector—The host interface programmer should change the host vector
(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt
control logic will receive a stable vector.
Cancelling a Pending Host Command Exception—The host processor may elect to clear the HC
bit to cancel the host command exception request at any time before it is recognized by the DSP.
Because the host does not know exactly when the exception will be recognized (due to exception
processing synchronization and pipeline delays), the DSP may execute the host command
exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the
same time that the HC bit is cleared.
Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL
lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make
sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then
polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ
together with the INIT and then polling INIT, ISR, and the HOREQ pin).
DSP Programming Considerations
Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF
status bits are set or cleared by the host processor side of the interface. These bits are individually
synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)
Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits
HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have
significance). A very small probability exists that the DSP will read the status bits synchronized
during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
相關(guān)PDF資料 |
PDF描述 |
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| SPB3 | RECTANGULAR CONNECTOR |
| SPB4 | RECTANGULAR CONNECTOR |
| SPB5 | RECTANGULAR CONNECTOR |
| SPBH5 | RECTANGULAR CONNECTOR |
| SPD16A1002AL13 | Thin Film Resistor Network Isolated and Bussed Circuits RoHS compliant available |
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