參數(shù)資料
型號(hào): SPC5604PEF0MLL6
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 54/104頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 100LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,F(xiàn)lexRay,LIN,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64K x 8
RAM 容量: 40K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 30x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 托盤
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
53
3.9
Power up/down sequencing
To prevent an overstress event or a malfunction within and outside the device, the MPC5604P implements the following
sequence to ensure each module is started only when all conditions for switching it ON are available:
A POWER_ON module working on voltage regulator supply controls the correct start-up of the regulator. This is a
key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5V. Associated
POWER_ON (or POR) signal is active low.
Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage
regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active.
A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active
high and released to all modules including I/Os, flash memory and RC16 oscillator needed during power-up phase and
reset phase. When POWER_OK is low the associated module are set into a safe state.
Figure 10. Power-up typical sequence
VIOLVDM5OK_H
P
I/O 5V low voltage detector high threshold
4.4
V
VIOLVDM5OK_L
P
I/O 5V low voltage detector low threshold
3.8
V
VMLVDDOK_H
P
Digital supply low voltage detector high
1.145
V
VMLVDDOK_L
P
Digital supply low voltage detector low
1.08
V
1 VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
Table 17. Low voltage monitor electrical characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Max
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR
0V
1.2V
0V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV)
3.3V
0V
POWER_OK
3.3V
RC16MHz Oscillator
0V
1.2V
P0
P1
0V
1.2V
Internal Reset Generation Module
FSM
~1us
VPOR_UP
VPORH
VLVDHV3H
VMLVDOK_H
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