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參數(shù)資料
型號: SPC5604PEF0MLL6
廠商: Freescale Semiconductor
文件頁數(shù): 76/104頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 100LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,F(xiàn)lexRay,LIN,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64K x 8
RAM 容量: 40K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 30x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 托盤
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
73
RSW110 — D Internal resistance of analog
source
VDD_HV_ADC =
5 V ± 10%
——
0.6
k
VDD_HV_ADC =
3.3 V ± 10%
——
3
k
RAD10 — D Internal resistance of analog
source
——
2
k
IINJ
— T Input current injection
Current injection on
one ADC input,
different from the
converted one.
Remains within TUE
spec.
–5
5
mA
INL
CC P Integral non-linearity
No overload
–1.5
1.5
LSB
DNL
CC P Differential non-linearity
No overload
–1.0
1.0
LSB
OSE
CC T Offset error
±1
LSB
GE
CC T Gain error
±1
LSB
TUE
CC P Total unadjusted error without
current injection
—–2.5
2.5
LSB
TUE
CC T Total unadjusted error with
current injection
—–3
3
LSB
1 VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage
from VSS_HV_ADCx to VDD_HV_ADCx.
2 VAINx may exceed VSS_HV_AD and VDD_HV_AD limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
3 Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1
4 Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0
5 AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
6 When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
7 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
8 This parameter includes the sample time tADC_S.
9 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
10 See Figure 15.
Table 31. ADC conversion characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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