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參數(shù)資料
| 型號： | SPC5604PEF0MLL6 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 68/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 512KB FLASH 100LQFP |
| 標準包裝： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心處理器： | e200z0h |
| 芯體尺寸： | 32-位 |
| 速度： | 64MHz |
| 連通性： | CAN，F(xiàn)lexRay，LIN，SPI，UART/USART |
| 外圍設備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 68 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 64K x 8 |
| RAM 容量： | 40K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 30x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
66
CJITTER T CLKOUT period
jitter6,7,8,9
Short-term jitter10
fSYS maximum
44
% fCLKOUT
Long-term jitter (avg.
over 2 ms interval)
fPLLIN = 16 MHz
(resonator)
, fPLLCLK at
64 MHz, 4,000 cycles
—10
ns
tlpll
D PLL lock time 11, 12
—
200
s
tdc
D Duty cycle of reference
—40
60
%
fLCK
D Frequency LOCK range
—
66
% fSYS
fUL
D Frequency un-LOCK range
—
-18
18
% fSYS
fCS
fDS
D Modulation depth
Center spread
±0.25
±4.013
% fSYS
Down spread
0.5
8.0
fMOD
D Modulation frequency14
—
70
kHz
1 VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
2 Considering operation with PLL not bypassed
3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked
mode.
4 Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
5 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6 This value is determined by the crystal manufacturer and board design.
7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
8 Proper PC board layout procedures must be followed to achieve specifications.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
13 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Table 29. FMPLL electrical characteristics (continued)
Symbol C
Parameter
Conditions1
Value
Unit
Min
Max
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SPC5604PEF0MLL7R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| SPC5604PEF0MLQ6 | 功能描述:32位微控制器 - MCU MPC5604P PICTUS 512K RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| SPC5604PEF0MLQ7R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| SPC5604PEF0VLL7R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| SPC5604PEF0VLQ7R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
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