參數(shù)資料
型號(hào)： SPL505YC256BTT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 20/27頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK CK505 BEARLAKE 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU，PCI Express（PCIe）
輸入： 晶體
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:22
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SPL505YC25
....................Document #: 001-03543 Rev *E Page 27 of 27
Document History Page
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon
Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of
information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters.
Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental
damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or
for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Silicon Laboratories harmless against all claims and damages.
Document Title: SPL505YC256BT/
SPL505YC256BS Clock Generator for Intel Bearlake Chipset
REV.
Issue Date
Orig. of
Change
Description of Change
1.0
12/13/06
JMA
New data sheet
1.1
1/30/07
JMA
1. Added SE1/SE2 to pinout in pinout diagram
2. Added clarifications to Byte 11
3. Added new definitions to Byte 13
4. Added PCI3/CFG0 voltage requirements in DC parameters
1.2
2/06/07
JMA
1. Changed Byte11 Bit 0 from 1 to 0; CPU2 to Stopped with CPU_STP#
2. Changed Byte 13 Bit 4 from 1 to 0; SATA spread default off
3. Changed Byte 13 Bit 2 from 0 to 1; SE drive strength default tohigh
4. Changed Byte 13 Bit 1 from 0 to 1; Reserved bit
6. Changed 1394A ppm from +/-100ppm to +/-30ppm
5. Added 1394B
6. Added CPU0 to CPU1 100ps skew spec
7. 25M typo on 1394A removed
8. FSD in overclocking description removed.
1.3
3/06/07
JMA
1. Part number changes due to part revision
2. Revision ID changed from 0000 to 0001 in Byte 7[7:4]
3. Added Byte 18 for additional single-ended drive strength control
1.4
3/21/07
JMA
1. Specified Triangular Spread Spectrum Profile
2. Removed IEEE clocks
3. RESERVED Byte 13 Bit5 - Engineering spread percentage -0.47%
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SPL505YC264BT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v0.85 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SPL505YC264BTT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v0.85 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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