參數(shù)資料
型號： SPL505YC256BTT
廠商： Silicon Laboratories Inc
文件頁數(shù)： 4/27頁
文件大?。?/td> 0K
描述： IC CLOCK CK505 BEARLAKE 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU，PCI Express（PCIe）
輸入： 晶體
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:22
差分 - 輸入:輸出： 無/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SPL505YC25
....................Document #: 001-03543 Rev *E Page 12 of 27
Byte 18 Control Register 18
The
SPL505YC256BT/
SPL505YC256BS requires a parallel resonance crystal.
Substituting
a
series
resonance
crystal
causes
the
SPL505YC256BT/
SPL505YC256BS
to operate at the wrong frequency and violate the ppm speci-
fication. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal sees must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. The common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal is
not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Bit
@Pup
Name
Description
7
0
PCI_DSC2
Drive Strength Control - DSC[2:0]
6
1
PCI_DSC0
5
0
USB_DSC2
4
0
USB_DSC0
3
0
SE1/SE2_DSC2
2
0
SE1/SE2_DSC0
1
0
REF_DSC2
0
REF_DSC0
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
DSC_2
(Byte18)
DSC_1
(Vario us B ytes)
DSC_0
(Byte 18)
Buffer
Strength
1
Strongest
11
0
10
1
10
0
Def ault PCI
01
1
Def ault REF/Usb
01
0
00
1
00
0
Weakest
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
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SPL505YC264BT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CK505 v0.85 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SPL505YC264BTT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CK505 v0.85 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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