參數(shù)資料
型號(hào)： SPL505YC256BTT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 5/27頁(yè)
文件大小： 0K
描述： IC CLOCK CK505 BEARLAKE 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU，PCI Express（PCIe）
輸入： 晶體
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:22
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SPL505YC25
....................Document #: 001-03543 Rev *E Page 13 of 27
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
Dial-A-Frequency (CPU & PCIEX)
This feature allows users to over-clock their systems by slowly
stepping up the CPU or SRC frequency. When the program-
mable output frequency feature is enabled, the CPU and SRC
frequencies are determined by the following equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G/M.
‘N’ and ‘M’ are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. ‘G’ stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See
Frequency Table for the Gear Constant for each Frequency
selection. The PCI Express only allows user control of the N
register, the M value is fixed and documented in the Frequency
Select Table.
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the required N value.
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0, (No
DAF).
CPU_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
Frequency Select Table.
CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the Frequency
Select Table.
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
SRC_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
Frequency Select Table.
Smooth Switching
The device contains 1 smooth switch circuit that is shared by
the CPU PLL and SRC PLL. The smooth switch circuit ensures
that when the output frequency changes by overclocking, the
transition from the old frequency to the new frequency is a
slow, smooth transition containing no glitches. The rate of
change of output frequency when using the smooth switch
circuit is less than 1 MHz/0.667
s. The frequency overshoot
and undershoot is less than 2%.
The Smooth Switch circuit can be assigned as auto or manual.
In Auto mode, clock generator will assign smooth switch
automatically when the PLL does overclocking. For manual
mode, the smooth switch circuit can be assigned to either PLL
via SMBus. By default the smooth switch circuit is set to auto
mode. Either PLL can still be over-clocked when it does not
have control of the smooth switch circuit but it is not
guaranteed to transition to the new frequency without large
frequency glitches.
It is not recommended to enable over-clocking and change the
N values of both PLLs in the same SMBUS block write and use
smooth switch mechanism on spread spectrum on/off.
PD# Clarification
The CK_PWRGD/PD# pin is a dual-function pin. During initial
power-up,
the
pin
functions
as
CK_PWRGD.
Once
CK_PWRGD has been sampled HIGH by the clock chip, the
pin
assumes
PD# functionality.
The PD#
pin
is an
asynchronous active LOW input used to shut off all clocks
cleanly prior to shutting off power to the device. This signal is
synchronized internal to the device prior to powering down the
clock synthesizer. PD# is also an asynchronous input for
powering up the system. When PD# is asserted LOW, all
clocks need to be driven to a LOW value and held prior to
turning off the VCOs and the crystal oscillator.
PD Assertion
When PS is sampled HIGH by two consecutive rising edges of
CPUC, all single-ended outputs will be held LOW on their next
HIGH-to-LOW transition and differential clocks must held
LOW. In the event that PD mode is desired as the initial
power-on state, PD must be asserted HIGH in less than 10
s
after asserting CK_PWRGD.
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
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