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參數(shù)資料
| 型號： | ST16C554DCJ68-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B QUAD 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 19 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC |
| 包裝： | 管件 |
| 其它名稱： | 1016-1265-5 |
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ST16C554/554D
19
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the
DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Reserved (Default 0)
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR BIT-7
FCR BIT-6
RECEIVE TRIGGER LEVEL
0
1
0
1
0
1
4
8
14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C554DCJ68TR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C554DCJ68TR-F | 功能描述:UART 接口集成電路 QUAD UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C554DCQ-0A-EB | 功能描述:界面開發(fā)工具 Supports C554D 64 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| ST16C554DCQ64 | 制造商:Exar Corporation 功能描述: |
| ST16C554DCQ64F | 制造商:Exar Corporation 功能描述: |
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