ST16C554/554D
33
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
TX
TXRDY#
IOW#
INT*
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
Data in
TX FIFO
Empty
T
WT
T
SI
TX FIFO
Empty
T
S
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when at least 1 byte is written to the TX FIFO.
T
WRI