參數(shù)資料
型號: ST16C554DCJ68-F
廠商: Exar Corporation
文件頁數(shù): 6/39頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B QUAD 68PLCC
標準包裝: 19
特點: *
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
規(guī)程: RS232
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: 1016-1265-5
ST16C554/554D
14
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
REV. 4.0.1
2.11
Internal Loopback
The 554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 10 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 10. INTERNAL LOOP BACK IN CHANNEL A AND B
TX A-D
RX A-D
M
ode
m
/
G
e
neral
Purp
ose
Co
ntro
lLogic
In
te
rn
al
Dat
a
Bu
s
Li
nes
an
d
Co
ntro
lSi
gn
als
RTS# A-D
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTS# A-D
DTR# A-D
DSR# A-D
RI# A-D
CD# A-D
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
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