參數(shù)資料
型號： ST16C554DCJ68-F
廠商： Exar Corporation
文件頁數(shù)： 2/39頁
文件大小： 0K
描述： IC UART FIFO 16B QUAD 68PLCC
標準包裝： 19
特點： *
通道數(shù)： 4，QUART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應商設備封裝： 68-PLCC
包裝： 管件
其它名稱： 1016-1265-5
ST16C554/554D
10
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
REV. 4.0.1
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following
table show their behavior. Also see Figure 17 through 22.
2.7
Crystal Oscillator or External Clock Input
The 554 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in Figure 4. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
generator for standard or custom rates. For further reading on oscillator circuit please see application note
DAN108 on EXAR’s web site.
2.8
Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) for the transmitter and receiver. The BRG further divides
this clock by a programmable divisor between 1 and (216 - 1) to obtain a 16X sampling rate clock of the serial
data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
The BRG divisor is unknown (DLL = 0xXX and DLM = 0xXX) and should be initialized after power up.
Programming the Baud Rate Generator Registers DLL and DLM provides the capability for selecting the
operating data rate. Table 6 shows the standard data rates available with a 14.7456MHz crystal or external
clock.
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR BIT-3 = 0
(DMA MODE DISABLED)
FCR BIT-3 = 1
(DMA MODE ENABLED)
RXRDY#
LOW = 1 byte
HIGH = no data
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
HIGH to LOW transition when FIFO reaches the
trigger level, or timeout occurs
LOW to HIGH transition when FIFO empties
TXRDY#
LOW = THR empty
HIGH = byte in THR
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS
C1
22-47pF
C2
22-47pF
14.7456
MHz
XTAL1
XTAL2
R=300K to 400K
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