REV. 5.0.3 3.0 UART CONFIGURATION REGISTERS The 650A has a set of configuration registers sel" />
參數(shù)資料
型號(hào)： ST16C650ACQ48-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 15/50頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 32B 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 32 字節(jié)
規(guī)程： 打印機(jī)，RS232，RS422，RS485
電源電壓： 2.9 V ~ 5.5 V
帶并行端口： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1662
ST16C650ACQ48-F-ND
ST16C650A
22
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.3
3.0 UART CONFIGURATION REGISTERS
The 650A has a set of configuration registers selected by address lines A0 to A2. The based page registers are
16C550 compatible with EXAR enhanced feature registers located on the second page (mirror) addresses.
The second page registers are only accessible by setting LCR register to a value of 0xBF. The register set is
shown on Table 7 and Table 8.
TABLE 7: ST16C650A UART CONFIGURATION REGISTERS
ADDRESS
REGISTER
READ/WRITE
COMMENTS
A2 A1 A0
16550 COMPATIBLE REGISTERS
0 0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 0
DLL - Divisor Latch Low
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DLM - Divisor Latch High
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0 0 0
DREV - Device Revision Code
Read-only
LCR[7] = 1, LCR
≠ 0xBF,
DLL, DLM = 0x00
0 0 1
DVID - Device Identification Code
Read-only
LCR[7] = 1, LCR
≠ 0xBF,
DLL, DLM = 0x00
0 0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0 1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR[7] = 0
0 1 1
LCR - Line Control Register
Read/Write
1 0 0
MCR - Modem Control Register
Read/Write
LCR[7] = 0
1 0 1
LSR - Line Status Register
Read-only
LCR[7] = 0
XFR - Extra Feature Register
Write-only
LCR[7] = 0, EFR[4] = 1
1 1 0
MSR - Modem Status Register
Read-only
LCR[7] = 0
IRPW - Infrared Pulse Width Register
Write-only
LCR[7] = 0, EFR[4] = 1
1 1 1
SPR - Scratch Pad Register
Read/Write
LCR[7] = 0
ENHANCED REGISTERS
0 1 0
EFR - Enhanced Function Register
Read/Write
LCR = 0xBF
1 0 0
Xon-1 - Xon Character 1
Read/Write
LCR = 0xBF
1 0 1
Xon-2 - Xon Character 2
Read/Write
LCR = 0xBF
1 1 0
Xoff-1 - Xoff Character 1
Read/Write
LCR = 0xBF
1 1 1
Xoff-2 - Xoff Character 2
Read/Write
LCR = 0xBF
.
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