REV. 5.0.3 2.90V TO 5.5V UART WITH 32-BYTE FIFO 2.10 Receiver The receiver section contains an 8-bit Receive Shift R" />
參數(shù)資料
型號： ST16C650ACQ48-F
廠商： Exar Corporation
文件頁數(shù)： 7/50頁
文件大小： 0K
描述： IC UART FIFO 32B 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點： *
通道數(shù)： 1，UART
FIFO's： 32 字節(jié)
規(guī)程： 打印機，RS232，RS422，RS485
電源電壓： 2.9 V ~ 5.5 V
帶并行端口： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1662
ST16C650ACQ48-F-ND
ST16C650A
15
REV. 5.0.3
2.90V TO 5.5V UART WITH 32-BYTE FIFO
2.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in the RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay
until it reaches the FIFO trigger level (XFR bit-3). Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.10.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 32 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE
R eceive D ata S hift
R egister (R SR )
Receive
D ata Byte
and Errors
R H R Interrupt (ISR bit-2)
Receive D ata
H olding R egister
(R HR)
RX F IFO 1
16X C lock
Receive Data Ch ara cters
D ata B it
Validation
E rror
T ags in
LS R bits
4:2
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