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參數(shù)資料
| 型號： | ST16C650ACQ48-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 19/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 32B 48TQFP |
| 標準包裝： | 250 |
| 特點： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 規(guī)程： | 打印機，RS232，RS422，RS485 |
| 電源電壓： | 2.9 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1662 ST16C650ACQ48-F-ND |
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ST16C650A
26
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.3
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH.
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table, Table 9, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level and TX FIFO empty (or transmitter empty in auto RS485 control).
MSR is by any of the MSR bits, 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of an Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
Wake-up Indicator: when the UART comes out of sleep mode.
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# status change interrupts are cleared by a read to the MSR register.
Wake-up Indicator is cleared by a read to the ISR register.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C650ACQ48TR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:ST16C650ACQ48TR-F |
| ST16C650AIJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650AIJ44-F | 功能描述:UART 接口集成電路 UART W/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C650AIP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650AIQ48 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:UART, 48 Pin, Plastic, TQFP |
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