- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385870 > ST6228CN3 (意法半導(dǎo)體) CB 5C 5#16S PIN RECP WALL PDF資料下載
參數(shù)資料
| 型號(hào)： | ST6228CN3 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CB 5C 5#16S PIN RECP WALL |
| 中文描述： | 8位單片機(jī)與微控制器/ D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書長(zhǎng)辦公室，安全復(fù)位和28引腳封裝 |
| 文件頁(yè)數(shù)： | 29/84頁(yè) |
| 文件大?。?/td> | 561K |
| 代理商： | ST6228CN3 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)當(dāng)前第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)
29/84
29
ST62T28C/E28C
INTERRUPTS
(Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable theindividual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 =
LES
: Level/Edge Selection bit
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
: Edge Selection bit
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4=
GEN
: Global Enable Interrupt When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive butcannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on the ST62E28C/
T28C are summarized in theTable 10 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 10. Interrupt Requests and Mask Bits
7
0
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
C8h
D4h
D1h
Mask bit
Masked Interrupt Source
Interrupt
source
All
source 4
source 4
GENERAL
TIMER
A/D CONVERTER
IOR
TSCR1
ADCR
GEN
ETI
EAI
RXIEN
TXIEN
OVIE
CPIE
EIE
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
ORPDn-DRPDn
All Interrupts, excluding NM
I
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY: Byte received
TXMT: Byte sent
OVF: ARTIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
End of Transmission
PAn pin
PBn pin
PCn pin
PDn pin
UART
UARTCR
D7h
source 4
ARTIMER
ARMC
E5h
source 3
SPI
Port PAn
Port PBn
Port PCn
Port PDn
SIDR
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
ORPD-DRPD
DCh
C0h-C4h
C1h-C5h
C2h-C6h
C3h-C7h
source 1
source 1
source 2
source 0
source 2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST6228CN6 | ER 5C 5#16S PIN RECP WALL |
| ST6391 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6392B1 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393B1 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6395B1 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6228CN3/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6228CN6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE |
| ST6228CN6/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST622X | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-Bit Micros |
| ST622XC-KIT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STARTER KIT DATASHEET FOR ST620X. ST621X AND ST622X |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。