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參數(shù)資料
| 型號(hào)： | ST6228CN3 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CB 5C 5#16S PIN RECP WALL |
| 中文描述： | 8位單片機(jī)與微控制器/ D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書(shū)長(zhǎng)辦公室，安全復(fù)位和28引腳封裝 |
| 文件頁(yè)數(shù)： | 30/84頁(yè) |
| 文件大?。?/td> | 561K |
| 代理商： | ST6228CN3 |
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ST62T28C/E28C
INTERRUPTS
(Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh
—
Read/Write
In conjunction with I/O register ESB bit, the polarity
of I/O pins triggered interrupts can be selected by
setting accordingly the Interrupt Polarity Register
(IPR). If a bit in IPR is set to one the corresponding
port interrupt is inverted (e.g. IPR bit 2 = A; port C
generates interrupt on rising edge. At reset, IPR is
cleared and allport interrupts are not inverted (e.g.
Port C generates interrupts on falling edges).
Bit 7 - Bit 4 = Unused
Bit 3 = Port D Interrupt Polarity.
Bit 2 = Port C Interrupt Polarity.
Bit 1= Port A Interrupt Polarity
Bit 0 = Port B Interrupt Polarity.
Tables 11. I/O Interrupts selections according to IPR, IOR programming
7
0
-
-
-
-
PortD PortC PortA PortB
GEN
IPR3
IPR0
IOR5
Port B occurrence
Port D occurrence
Interrupt
source
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
2
GEN
IPR1
IOR6
Port A occurrence
Interrupt
source
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
falling edge
low level
rising edge
high level
Disabled
1
IPR2
0
1
Port C occurrence
falling edge
rising edge
Interrupt source
0
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