參數(shù)資料
型號(hào)： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 104/144頁(yè)
文件大?。?/td> 1280K
代理商： ST72774S9T1/XXX
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ST72774/ST727754/ST72734
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SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6.3 Detecting Signal Polarity
The Sync Processor provides two ways for
checking input signal polarity by polling the latches
or using the 5-bit up/down counter.
Polling check
– HSYNCI polarity detection:
UPLAT/DWNLAT bits in LATR register
These bits are directly connected to the 5-bit
Up/Down counter.
UPLAT=1/ DOWNLAT=0 HSYNCI polarity<0
UPLAT=0/ DOWNLAT=1 HSYNCI polarity>0
– VSYNCI Polarity Detection
– VPOL bit (VSYNCO polarity) in POLR and
– VOP bit (VSYNCO polarity control) in MCR
The delay between VSYNCI polarity changes
and the VPOL bit typically toggles within 4
msecs. The polarity detector includes an
integrator to filter possible incoming VSYNCI
glitches.
5-bit Up/Down Counter Check
for HSYNCI Polarity
This method involves the internal 5-bit up/down
counter.
The counter value (CV4-CV0 bits) is updated with
the 5-bit counter value at every detected edge on
the signal monitored.
It is incremented when the signal is high, otherwise
it is decremented.
– Start the detection phase:
Initialize the 5-bit counter: write '00000' in the
CCR register (CV4-CV0 bits).
Select normal mode on falling edge:
LCV1/LCV0 = 0 in the CCR register.
– Software checks the counter value (CV4-CV0)
after an interrupt (with the signal internally con-
nected or ICAP2) or by polling (timeout 150s).
Positive polarity: The counter value < 1Fh.
Negative polarity: The counter value =1Fh on
the falling edge.
In case of a composite incoming signal, the
software just has to check that the VSYNCO
period and polarity are stable.
4.4.6.4 Extracting VSYNCO from CSYNCI
In case of composite sync, the Vertical sync output
signal is extracted with the 5-bit up/down counter.
Initially,
the
width
of
an
Horizontal
Sync
component pulse is automatically determined by
hardware which defines a threshold for the 5-bit
counter with a possible user-defined tolerance.
The circuit then monitors for any incoming period
greater than this previously captured value. This is
then processed as the VSYNCO signal.
To use the Vsync extractor, the following steps are
necessary:
– Detection of a composite sync signal:
When the UPLAT and DOWNLAT bits in LATR
register are set, a composite sync signal or a
HSYNCI polarity change is detected.
If these bits are stable during two subsequent
ICAP2 interrupt, the composite sync signal is
stable.
– Defining a threshold:
Select the normal mode (LCV1/LCV0=0 in the
CCR register).
Initialize the counter capture CV4-CV0 to 0.
This automatically measures the HSYNCI pulse
width. It defines a threshold in the CV4-CV0 bits
used by the 5-bit up/down counter.
It also allows to check the HSYNCI polarity
(refer to the “5-bit Up/Down Counter Check”
paragraph.
If a user-defined tolerance is to be added, then
an updated value should be written in the CCR
register (CV4-CV0 bits).
In a composite sync signal, Hsync and Vsync
always have the same polarity.
– Starting the VSYNCO hardware extraction
mode:
According to the Composite sync polarity, select
the extraction mode (LCV1/LCV0 in CCR
register) and rewrite the counter if necessary.
Negative polarity: minimum threshold (00h)
Positive polarity: maximum threshold (1Fh)
Note:
The
extracted
VSYNCO
signal
always
has
negative polarity.
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