參數(shù)資料
型號： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁數(shù)： 137/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1/XXX
ST72774/ST727754/ST72734
92/144
IC SINGLE MASTER BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF
Event flag.
This bit is set by hardware as soon as an event
occurs. It is cleared by software reading SR2
register in case of error event or as described in
Figure 54. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– SB=1 (Start condition generated)
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
– Address byte successfully transmitted.
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA
Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware when the
interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = BTF
Byte transfer finished.
This bit is set by hardware as soon as a byte is
correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software
reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when
the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV2 event (See Figure 54). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1 = M/IDL
Master/Idle.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after generating a Stop condition on
the bus. It is also cleared when the interface is
disabled (PE=0).
0: Idle mode
1: Master mode
Bit 0 = SB
Start bit generated.
This bit is set by hardware as soon as the Start
condition
is
generated
(following
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled
(PE=0).
0: No Start condition
1: Start condition generated
70
EVF
0
TRA
0
BTF
0
M/IDL
SB
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