參數(shù)資料
型號(hào)： ST72774S9T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： TQFP-44
文件頁數(shù)： 7/144頁
文件大小： 1280K
代理商： ST72774S9T1/XXX
ST72774/ST727754/ST72734
104/144
DDC INTERFACE (Cont’d)
EDID Data structure mapping: An internal
address pointer defines the memory location being
addressed. It is made of two 8-bit registers AHR
and ALR.
AHR is initialized by software. It defines the 256-
byte
block
within
the
64K
address
space
containing the data structure.
ALR is loaded with the data address sent by the
master after a write Device Address. It defines the
byte within the data structure currently addressed.
ALR is reset upon entry into the DDC2B mode.
One exception to this arrangement is when the
CF[1:0] bits = 10b. In this case the two EDID
versions
must
coexist
at
non-overlapping
addresses. The LSB of AHR is therefore ignored
and automatically set to 1 to address the 128-byte
EDID and set to 0 to address its 256-byte
counterpart (see Figure 64).
Figure 64. Mapping of DDC2B data structure
AHR
ALR
0
7
8
15
Addr Pointer
0000h
FFFFh
128-byte Data
2
56
b
ytes
Structure
0000h
FFFFh
256
byte
s
0000h
FFFFh
ALR
256-byte Data
256
byte
s
Structure
128-byte Data
Structure
A0h/A1h
A2h/A3h + A6h/A7h
0000h
FFFFh
128-byte Data
256
bytes
Structure
0000h
FFFFh
256
bytes
0000h
FFFFh
ALR
256-byte Data
256
b
ytes
Structure
128-byte Data
Structure
A0h/A1h
A2h/A3h
AHR<7:1>
ALR
0
7
8
15
Addr Pointer
9
1
AHR<7:1>
ALR
0
7
8
15
Addr Pointer
9
0
512
AHR<7:1>
*
256
AHR
*
DDC v2 + P&D mode: CF[1:0] bits = 10b
DDC v2 / P&D / FPDI-2 modes: CF[1:0] bits != 10b
Extended EDID v1 (if present)
Basic EDID v1
Extended EDID v1 (if present)
Basic EDID v1
EDID v2
ALR :
80h -> FFh
ALR :
80h -> FFh
ALR :
00h -> 7Fh
ALR :
00h -> 7Fh
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