參數(shù)資料
型號(hào): ST72E85A5G0
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封裝: WINDOWED, CERAMIC, QFP- 80
文件頁數(shù): 27/117頁
文件大?。?/td> 748K
代理商: ST72E85A5G0
17/117
ST7285C
3.2 MISCELLANEOUS REGISTER
The Miscellaneous register allows one to select
the SLOW operating mode and to set the clock di-
vision prescaler factor. Bits 3 and 4 allow one to
set PB7 functionality (I/O, CPU Clock o/p or Beep
signal o/p), while bits 6 and 7 determine the signal
conditions which will trigger an interrupt request on
I/O pins having interrupt capability.
Register Address: 0020h
Read/ Write
Reset Value: 00h
b7, b6 - EI1, EI0:
External Interrupt Option
0 0 - Negative edge and low level (Reset state)
1 0 - Negative edge only
0 1 - Positive edge only
1 1 - Positive and negative edge
This selection applies globally to the four external
interrupts: I1, I2, I9 and I10.
b6 and b7 can be written only when the Interrupt
Mask (I) of the CC (Condition Code) register is set
to 1.
b5- Reserved
b4, b3 - SK1, CK0
: Clock/Beep Output
0 0 - I/O port (Reset state)
1 0 - I/O port
0 1 - CPU Clock output to pin PB7
1 1 - 2KHz Beep signal output to pin PB7
(at 8.664 MHz oscillator frequency)
b2, b1 - SM1,SM0:
CPU clock prescaler for Slow
Mode
0 0 - Oscillator frequency / 4
1 0 - Oscillator frequency / 8
0 1 - Oscillator frequency / 16
1 1 - Oscillator frequency / 32
b0 - SMS: Slow Mode Select
0- Normal mode - Oscillator frequency / 2
(Reset state)
1- Slow mode (Bits b1 and b2 define the prescaler
factor)
70
EI1
EI0
b5
SK1
CK0
SM1
SM0
SMS
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