- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98145 > ST72E85A5G0 (STMICROELECTRONICS) 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 PDF資料下載
參數(shù)資料
| 型號： | ST72E85A5G0 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 |
| 封裝： | WINDOWED, CERAMIC, QFP- 80 |
| 文件頁數(shù)： | 47/117頁 |
| 文件大?。?/td> | 748K |
| 代理商： | ST72E85A5G0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
35/117
ST7285C
4.3 16-BIT TIMER
4.3.1 Introduction
One or more Timers may be present in the MCU,
depending on product specification. Please refer
to the Block Diagram to ascertain available prod-
uct resources, and to the Memory Map for register
addresses.
Each timer consists of a 16-bit free-running coun-
ter driven by a programmable prescaler, as well as
the control logic required to implement two input
capture and two output compare registers. The
timer may be used for a variety of purposes,
amongst which pulse length measurement of up to
two input signals and generation of up to two out-
put waveforms (e.g. PWM). The Timer Block Dia-
gram is illustrated in Figure 1.
Pulse lengths and waveform periods can vary from
a few microseconds to many seconds, thanks to
the programmable prescaler. When running with a
4MHz internal CPU clock, the timer can have a
resolution of 0.5, 1 or 2
s, depending on the set-
ting of the clock control bits in the Timer Control
Register (TCR2). A software selectable external
clock input pin is available.
Since the timer has a 16-bit architecture, each of
its specific functional blocks is associated with a
register pair. These registers contain the high or-
der byte and the low order byte respectively of the
related function. Access to the high order byte in-
hibits the associated timer function until the low or-
der byte is also accessed.
Correct software procedures should set bit ‘I’ of
the Condition Code Register before accessing the
high order byte to prevent an interrupt from occur-
ring between accesses to the high and low order
bytes of any register.
In normal operating mode, reading the MSB of the
Input Capture register inhibits Input Capture until
the LSB is read. This mechanism allows Input cap-
ture to be disabled when the pin is connected to an
I/O bit.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) features are selected to-
gether, the PWM mode is the only active one.
4.3.2 Counter
The key element of the Programmable Timer is a
16-bit free running counter and its associated reg-
ister. The counter is preceeded by a prescaler
which divides the internal clock by two, four or
eight, depending on the setting of the clock control
bits of the Timer Control Register (TCR2), as illus-
trated in Table 1 below.
Table 7. Clock Control Bits
Software can read the counter at any time without
affecting its value, either from the Counter Regis-
ters or from the Alternate Counter Registers. The
only difference between these two read-only regis-
ter pairs is the way the overflow flag (TOF) is han-
dled during a read sequence.
A read sequence where only the least significant
byte of the free running counter is read (from either
the Counter Register or the Alternate Counter
Register), will receive the LSB of the count value
at the time of the read.
A read of the most significant byte (from either the
Counter Register or the Alternate Counter Regis-
ter) simultaneously returns the MSB of the count
value and causes the LSB to be transferred to a
buffer. The buffered value remains unchanged un-
til the 16-bit read sequence is completed, even if
the user reads the MSB several times. The read
sequence is completed by reading the LSB, which
actually returns the buffered value.
As shown in Figure 2, Figure 3 and Figure 4, the
free-running counter is set to FFFCh on Reset.
During a Power-On Reset (POR) cycle, the coun-
ter is loaded with FFFCh and begins running.
CC1
CC0
Clock Divisor
00
4
01
2
10
8
1
External Clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72F321J9T7 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321J7T3 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321J7T1 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321J9T5 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F324BJ6B6 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72F260G1B5 | 功能描述:8位微控制器 -MCU Flask 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F260G1M6 | 功能描述:8位微控制器 -MCU Flash 4K SPI/I2C/SCI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F260G1M6/TR | 功能描述:8位微控制器 -MCU 8B MCU FLASH OR ROM MEMORY RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F262G1B5 | 功能描述:8位微控制器 -MCU Flask 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F262G1B6 | 功能描述:8位微控制器 -MCU 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。