參數(shù)資料
型號： ST72E85A5G0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封裝： WINDOWED, CERAMIC, QFP- 80
文件頁數(shù)： 40/117頁
文件大?。?/td> 748K
代理商： ST72E85A5G0
29/117
ST7285C
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
Each receiving device decodes this address head-
er under program control and all non addressed
receivers may be placed in a sleep mode by
means of the Muting function, thus avoiding the
message contents from generating unnecessary
requests for service. This is achieved by inhibiting
all reception flags and interrupt generation when
Muting is enabled. A muted receiver may be re-
awakened in one of two ways: by Idle Line detec-
tion or by Address Mark detection. The wake-up
method may be programmed by programming the
WAKE bit in the SCCR1 register.
Receiver wake-up by Idle Line detection takes
place as soon as the Receive line is recognised as
being idle. An Idle Line condition is detected upon
receiving 10 or 11 consecutive ”ones”, depending
on whether a word has been defined as compris-
ing 8 or 9 data bits. This wake-up method is select-
ed by programming the WAKE bit to ”0”.
Receiver wake-up by Address Mark detection
takes place on receiving a ”1” as the most signifi-
cant bit of a word, thus indicating that the message
is an address. This wake-up method is selected by
programming the WAKE bit to ”1”.
4.2.6 Baud Rate Generation
The following description is best read with refer-
ence to the SCI Baud Rate and External Prescaler
Diagram illustrated in Figure 2.
The CPU Clock is first divided by 16 by the first di-
visor block, then again divided by the division fac-
tor selected for the first prescaler, indicated by PR.
This division factor can be selected to be 1, 3, 4 or
13, depending on the setting of the SCP0 and
SCP1 bits (bits 6 and 7) in the SCBRR register (re-
fer to the register description). The output from the
first prescaler will thus be the CPU Clock frequen-
cy divided by 16, 48, 64 or 208. This master clock
is available both to the conventional Baud Rate
Generator and to the External Prescaler.
The conventional Baud Rate Generator is enabled
by setting the relevant section (RX or TX) of the
External Prescaler to 00h. In this case the master
clock frequency is further divided by 1, 2, 4, 8, 16,
32, 64 or 128, depending on the settings of bits
SCT0, SCT1 and SCT2 in the case of the transmit-
ter, and SCR0, SCR1 and SCR2 in the case of the
receiver (refer to the SCBRR register description).
If the External Prescaler Receive or Transmit
Baud Rate Register, PSBRT or PSBRR is set to a
value other than zero, that section of the prescaler
will be operational in place of the conventional
Baud Rate Generator. The output clock rate sent
to the transmitter or to the receiver will be the out-
put from the first prescaler divided by a factor
ranging from 1 to 255 set in the External Prescaler
Receive or Transmit Baud Rate Register. As can
be seen the External Prescaler option gives a very
fine degree of control on the Baud rate, whereas
the conventional Baud Rate Generator retains in-
dustry standard software compatibility.
4.2.7 SCI Register Overview
The registers described in the following para-
graphs allow full control of the various features
and parameters of the Serial Communications In-
terface. Refer also to the Memory Map.
4.2.7.1 Data Register (SCDR)
Address: 0051h
—
Read/Write
Reset Value: XXh
Contains the Received or Transmitted data char-
acter, depending on whether it is read or written to.
4.2.7.2 Control Register 1 (SCCR1)
Address: 0053h
—
Read/Write
Reset Value: XXh
Contains bits to select the desired word length and
the wake-up mode.
Bit-7 = R8
Receive Data Bit 8
If bit M is set at one, R8 will be used to store the
9th bit on reception.
Bit-6 = T8
Transmit Data Bit 8
Used to store the 9th data bit of the transmitted
word, when 9-bit word length is selected (bit M set
to ”1”).
Bit-4 = M
Word Length
Determines the word length:
0 = 1 Start bit, 8 Data bits, 1 Stop bit
1 = 1 Start bit, 9 Data bits, 1 Stop bit
Bit-3 = WAKE
Wake-Up Method
1 = Address Mark
0 = Idle Line
76
5
43210
R8
T8
-
M
WAKE
-
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