參數(shù)資料
型號: ST72E85A5G0
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封裝: WINDOWED, CERAMIC, QFP- 80
文件頁數(shù): 31/117頁
文件大?。?/td> 748K
代理商: ST72E85A5G0
20/117
ST7285C
3.5 INTERRUPTS
A list of interrupt sources is given inTable 5 below,
together with relevant details for each source. In-
terrupts are serviced according to their order of pri-
ority, starting with I0, which has the highest priori-
ty, and so to I11, which has the lowest priority.
The following list describes the origins for each in-
terrupt level:
– I0 connected to Software Interrupt (TRAP)
– I1 connected to Port G3
– I2 connected to Port F0, F1, F2, F3
– I3 connected to SPI A
– I4 connected to Timer A
– I5 connected to GBS interrupt
– I6 connected to Timer B
– I7 connected to SPI B
– I8 connected to SCI
– I9 connected to Ports D4, D5
– I10 connected to Ports C4, C5
– I11 connected to I
2C
Exit from HALT mode may only be triggered by an
External Interrupt on one of the following ports:
C4(I10), C5(I10), D4(I9), D5(I9), F0(I2), F1(I2),
F2(I2), F3(I2) and G3(I1).
If more than one input pin of a group connected to
the same interrupt line is selected simultaneously,
these will be logically ORed.
Table 5. Interrupt Mapping
Interrupt
source
Vector
Address
Interrupts
Register
Flag
name
CPU
interrupts
-
FFFEh-FF FFh
Reset
N/A
RESET
I0
FFFCh-FFFDh
Software
N/A
TRAP
I1
FFFA h-FFFBh
Ext. Interrupt (Port G3)
N/A
INT1
I2
FFF8h-FFF 9h
Ex. Interrupt (Ports F0, F1, F2, F3)
N/A
INT2
I3
FFF6h-FFF 7h
Transfer Complete
SPI A Status
SPIF1_A
SPI_A
Mode Fault
MODF1_A
I4
FFF4h-FFF 5h
Input Capture 1
Timer A Status
ICF1_A
TIMER_A
Output Compare 1
OCF1_A
Input Capture 2
ICF2_A
Output Compare 2
OCF2_A
Timer Overflow
TOF_A
I5
FFF2h-FFF 3h
RDS Block Interrupt.
RDS GRP
VSI
CNI
GBS
I6
FFF0h-FFF 1h
Input Capture 1
Timer B Status
ICF1_B
TIMER_B
Output Compare 1
OCF1_B
Input Capture 2
ICF2_B
Output Compare 2
OCF2_B
Timer Overflow
TOF_B
I7
FFEEh-FFEFh
Transfer Complete
SPI B Status
SPIF2_B
SPI_B
Mode Fault
MODF1_B
I8
FFECh-FFEDh
Transmit Buffer Empty
SCI Status
TDRE
SCI
Transmit Complete
TC
Receive Buffer Full
RDRF
Idle Line Detect
IDLE
Overrun
OR
I9
FFEAh-FFE Bh
Ext. Interrupt (Ports D4,D5)
N/A
INT9
I10
FFE8h-FFE9h
Ext. Interrupt (Port C4, C5)
N/A
INT10
I11
FFE6h-FFE7h
Byte Transmission Finished
I2C Status
BTF
I2C
Bus Error
BERR
I2C
Stop Detection
SSTOP
I2C
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