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參數(shù)資料
| 型號(hào)： | ST92195D7T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁(yè)數(shù)： | 202/250頁(yè) |
| 文件大?。?/td> | 3010K |
| 代理商： | ST92195D7T1/XXX |
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ST92195 ST92T195 ST92E195 - INTERRUPTS
3.9 INTERRUPT RESPONSE TIME
The interrupt arbitration protocol functions com-
pletely asynchronously from instruction flow and
requires 5 clock cycles. One more CPUCLK cycle
is required when an interrupt is acknowledged.
Requests are sampled every 5 CPUCLK cycles.
If the interrupt request comes from an external pin,
the trigger event must occur a minimum of one
INTCLK cycle before the sampling time.
When an arbitration results in an interrupt request
being generated, the interrupt logic checks if the
current instruction (which could be at any stage of
execution) can be safely aborted; if this is the
case, instruction execution is terminated immedi-
ately and the interrupt request is serviced; if not,
the CPU waits until the current instruction is termi-
nated and then services the request. Instruction
execution can normally be aborted provided no
write operation has been performed.
For an interrupt deriving from an external interrupt
channel, the response time between a user event
and the start of the interrupt service routine can
range from a minimum of 26 clock cycles to a max-
imum of 55 clock cycles (DIV instruction), 53 clock
cycles (DIVWS and MUL instructions) or 49 for
other instructions.
For a non-maskable Top Level interrupt, the re-
sponse time between a user event and the start of
the interrupt service routine can range from a min-
imum of 22 clock cycles to a maximum of 51 clock
cycles (DIV instruction), 49 clock cycles (DIVWS
and MUL instructions) or 45 for other instructions.
In order to guarantee edge detection, input signals
must be kept low/high for a minimum of one
INTCLK cycle.
An interrupt machine cycle requires a basic 18 in-
ternal clock cycles (CPUCLK), to which must be
added a further 2 clock cycles if the stack is in the
Register File. 2 more clock cycles must further be
added if the CSR is pushed (ENCSR =1).
The interrupt machine cycle duration forms part of
the two examples of interrupt response time previ-
ously quoted; it includes the time required to push
values on the stack, as well as interrupt vector
handling.
In Wait for Interrupt mode, a further cycle is re-
quired as wake-up delay.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST92195D5T1/XXX | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92195C8T1/XXX | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92195C6B1/XXX | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST92195C4B1/XXX | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST9291N3 | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92196A | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8/16-BIT MCU FOR TV APPLICATIONS WITH UP TO 96K ROM, ON-SCREEN-DISPLAY AND 1 OR 2 DATA SLICERS |
| ST92196A2B1/JPR | 制造商:STMicroelectronics 功能描述: |
| ST92196A4B1 | 制造商:STMicroelectronics 功能描述: |
| ST-922 | 制造商:UNBRANDED 功能描述:MULTIMETER DIGITAL |
| ST9250410AS | 制造商:Seagate Technology 功能描述:250GB 2.5" Momentus 5400.6 Mobile Hard Drive 制造商:Seagate Technology 功能描述:250GB 2.5" SATA Hard Drive 7200RPM |
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