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參數(shù)資料
| 型號： | ST92195D7T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 241/250頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | ST92195D7T1/XXX |
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ST92195 ST92T195 ST92E195 - TELETEXT DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.3 Initialisation
7.3.3.1 Clock Initialisation
Before initialising the TRI, first initialise the pixel
clock. Refer to the Application Examples in the
OSD chapter and to the RCCU chapter for a de-
scription of the clock control registers.
7.3.3.2 TRI Initialisation
It is recommended to wait for a stable clock issued
from the Pixel frequency multiplier before enabling
the TDSRAM interface.
Use the CONFIG register to initialise and start
the TRI and Acquisition units. Note: The AON and
DON bits can only be changed while GEN=0
Example:
spp #0x26
ld config, #0x06 ; AON,DON,GEN=0
or config, #0x01 ; set GEN=1
During and after a reset, the TDSRAM interface is
forced into its "disable" mode where the sequencer
is forced into its idle state.
7.3.3.3 Multi-Byte Transfer (MBT) Initialisation
A multi-byte transfer corresponds to a 40-byte ex-
change between the RAM and an internal 40-byte
buffer located into the TDSRAM interface. This
buffer is register-mapped and can be directly ac-
cessed by the CPU in its register page space.
Start the MBT transfer by setting the BUSY bit in
the BUFC register.
Example:
spp #0x26
ld BUFC, #0x01 ;
;Start DMA transfer
;Poll on Busy bit
The exchange can be either a read (extraction of
40 consecutive bytes from the RAM starting at a
software programmed address) or a write (writing
of 40 consecutive bytes to the RAM starting at a
software programmed address). The address is a
13 bit-long word allowing access to any TDSRAM
location. The address can be either incremented
or decremented depending on a control bit.
While the transfer is running, the buffer is no long-
er software accessible ("busy bit" (BUFC.0) is set
to 1). Once the exchange is completed, this bit is
automatically reset and the MBT slots are auto-
matically given back to the CPU.
Four powerful data exchange modes are provided:
– Read only (transfer from the RAM to the buffer)
– Write only (transfer from the buffer to the RAM)
– Write with parity reject (if the byte presents a par-
ity error, it will not be written into the TDSRAM;
the corresponding location keeps its previous
content).
– Parity cancelled on write (the MSB is replaced by
"0" when the byte is written into the TDSRAM).
The "parity reject" and "parity cancelled" modes
can be used simultaneously during a write opera-
tion. In this case, the parity check will be done first
and the parity bit will be removed, if the write oper-
ation has to be performed. The parity check per-
formed is the following:
– The parity is correct when the number of 1s (cur-
rent byte) is an odd number.
– The parity is incorrect when the number of 1s
(current byte) is an even number.
A parity check flag (BUFC.5) is provided for the
whole buffer. This bit is set when a parity error is
detected during the write operation. This bit has to
be reset by software before starting another MBT.
7.3.3.4 100/120 Hz Applications
In 100/120 Hz applications, both the vertical and
horizontal beam scanning speeds are doubled
while the CVBS signal remains unchanged. To
handle this, the EOFVBI interrupt can be delayed
from the beginning of deflection line 25 to the be-
ginning of line 50 by setting the DS bit of the CON-
FIG register. If the DS bit is set, the interrupt is only
generated when the complete Teletext data is fully
sliced and stored.
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