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參數(shù)資料
| 型號： | ST92195D7T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 98/250頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | ST92195D7T1/XXX |
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ST92195 ST92T195 ST92E195 - TWO-CHANNEL I2C BUS INTERFACE (I2C)
I2C BUS INTERFACE (Cont’d)
7.10.3.2 Slave Mode
As soon as a start condition is detected, the ad-
dress is received from the SDA line and sent to the
shift register; then it is compared with:
– The 7 MSB of the interface address (see
I2COAR register) if the ADR0 bit = 0
– The 4 MSB of the interface address (see
I2COAR register) if the ADR0 bit = 1
– The General Call address
Address not matched: the interface ignores it
and waits for another Start condition.
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the GENC_ACK bit
(I2CCTR register) is set and a general call is de-
tected, or if the SEND_ACK bit (I2CCTR register)
is reset and “normal” address if detected.
– An interrupt is generated and the INT bit of the
I2CSTR2 register is set.
Then check the I2CSTR1 register to know the in-
terface status:
– Read the FIRST bit of the I2CSTR1 register to
know whether the byte stored in the I2CDR reg-
ister is the address (first byte transferred in an
I2C transaction) or a data.
– If the GEN_CALL bit is set, a general call has
been requested by a master.
– If the ACT_SLV bit is set and the READ bit is set,
the interface is an active slave transmitter, else,
if the ACT_SLV bit is set and the READ bit is re-
set, the interface is an active slave receiver.
Slave receiver
After the address, the slave receives bytes from
the SDA line into the I2CDR register via the inter-
nal shift register. After each received byte the in-
terface generates in sequence:
– Acknowledge pulse according to the
SEND_ACK bit value
– An interrupt is generated and the INT bit of the
I2CSTR2 register is set.
Using the FIRST bit of the I2CSTR1 register, you
know whether the byte stored in the I2CDR regis-
ter is the address (first byte transferred in an I2C
transaction) or data.
Slave Transmitter
Following the address reception, the slave sends
bytes from the DR register to the SDA line via the
internal shift register.
The slave writes in the I2CDR register the data to
send on the SDA bus.
When the acknowledge pulse is received:
– an interrupt is generated and the INT bit of the
I2CSTR2 register is set.
Then you need to check the ACK_BIT of the
I2CSTR2 register to know whether the last byte
has been acknowledged or not. If some data have
to be sent again, write the value in the OSDDR
register.
Closing a slave communication
The I2C interface returns to inactive slave state as
soon as a stop condition has been detected.
If the ISCEN bit of the I2CSTR2 is set, an interrupt
is generated on detecting the stop condition, al-
lowing the user to know if the transaction was suc-
cessful by checking the ERROR and ACTIVE flags
of the I2CSTR1 register.
7.10.3.3 Master Mode
To switch from default inactive slave mode to Mas-
ter mode: load a slave address in the I2CDR reg-
ister.
If the bus is free (ACTIVE bit of the I2CSTR2 reg-
ister reset), then the I2C interface automatically
generates a start condition followed by the I2CDR
byte.
Then, on the 9th clock pulse, an interrupt is gener-
ated and the INT bit of the I2CSTR2 register is set.
Check the ACK_BIT bit of the I2CSTR1 register to
know whether the slave address has been ac-
knowledged or not, in order to manage the trans-
action.
If needed, generate a stop condition on the bus
with the STOP bit of the I2CSTR1 register.
Note: If the RSRT bit of the I2CCTR register is set,
the master will generate a repeated start se-
quence as soon as a new byte is loaded in the
I2CDR register.
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