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ST92195 ST92T195 ST92E195 - VPS & WSS SLICER
VPS & WSS SLICER (Cont’d)
VPS DATA REGISTER 3 (VPSD3R)
R244 - Read Only
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7:2 = ASM[5:0]:
Announced start of item,
MINUTE.
Bit 1:0 = NC[3:2]: Nationality code which is used
to identify the source of the item.
VPS DATA REGISTER 4 (VPSD4R)
R245 - Read Only
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7:6 = NC[1:0]: Nationality code which is used
to identify the source of the item.
Bit 5:0 = PS[5:0]:
Program source code used to
identify the source of the item inside the country
identified in the nationality code.
WSS
DATA
AND
STATUS
REGISTER
0
(WSSDS0R)
R246 - Read Only
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7 = Reserved.
Bit 6 = NWDATWS:
New data in all three data reg-
isters. Data will be written into this register with or
without bi-phase errors. The error bit for each byte
of data should be checked to validate any data.
Reset by writing to this register or by the leading
edge of Wss Window. This flag will only be set
when the number of bits saved is correct for the
time expected for those bits.
Bit 5= VFRMWSS:
Valid Framing code for WSS.
This bit is set when the framing code is error free.
Reset by the end of WSS Window.
Bit 4 = GP1ERF: This bit is set when any of the
Group 1 bits (WSS3-0) are received with a bi-
phase error.
b3-b0 = WSS3-0:
WSS Aspect Ratio Bits
WSS
DATA
AND
STATUS
REGISTER
1
(WSSDS1R)
R247 - Read Only
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7 = WSS2X: WSS has been received 2X (2
times). This bit is set when a second line of WSS
has been saved in registers VPS0A - VPS0C.
Bit 6:5 = Reserved.
Bit 4 = GP2ERF: This bit is set when any of the
Group 2 bits (WSS[3:0]) is received with a bi-
phase error.
Bit 3:0 = WSS[7:4]: WSS Enhanced Service Bits.
WSS
DATA
AND
STATUS
REGISTER
2
(WSSDS2R)
R248 - Read Only
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7 = GP3ERF: This bit is set when any of the
Group 3 bits (WSS[3-0]) are received with a bi-
phase error.
Bit 6:4 = WSS[10:8]: WSS Subtitle Bits
Bit 3 = GP4ERF: This bit is set when any of the
Group 4 bits (WSS[3:0]) are received with a bi-
phase error.
Bit 2:0 = Reserved Bits
70
ASM5 ASM4 ASM3
ASM2
ASM1
ASM0
NC3
NC2
70
NC1
NC0
PSC5
PSC4
PSC3
PSC2
PSC1 PSC0
70
x
NWDA
TWS
VFRM
WS
GP1ER
F
WSS3
WSS2
WSS1 WSS0
70
WSS2
X
xx
GP2ER
F
WSS3
WSS2
WSS1 WSS0
70
GP3ERF WSS10 WSS9
WSS8
GP4ERF
x